The present invention relates to a device and a method for performing an error detection operation and a sync detection operation when formatting digital data.
In downstream transmissions for Internet communications using cable modems or for CATV broadcasting in North America and other regions, a data format that is in compliance with the ITU-T J.83 ANNEX B specification is used. According to this specification, packet data including Reed-Solomon decoded data where 1 byte is comprised of 7 bits is converted to a transport stream data packet where 1 byte is comprised of 8 bits. In this process, it is necessary to perform a sync byte detection operation, an error detection operation, and a transport stream sync byte insertion operation for the 7-bit data packet. The series of operations for converting packet data including Reed-Solomon decoded data where 1 byte is comprised of 7 bits to a transport stream data packet where 1 byte is comprised of 8 bits will hereinafter be referred to as an “MPEG framing process”.
The MPEG framing process is shown in detail in ITU-T Recommendation J.83, ANNEX B, Digital multi-program System B, B.4 MPEG-2 transport framing. Particularly, Figure B.3/J.83 shows an actual decoding circuit. The circuit is a syndrome computation circuit for performing the sync byte detection operation.
The specification of the circuit is such that the circuit receives data that is obtained by converting the 7-bit byte Reed-Solomon decoded data to serial bits, and performs a syndrome computation operation using the serial data so as to perform a parity check operation for error detection and to simultaneously perform a sync byte detection operation according to the result of the parity check operation. Then, after performing the parity check operation and the sync detection operation in a serial process, the output data is converted to 8-bit byte data where 1 byte is comprised of 8 bits, thus providing a transport stream data packet.
Typically, the parity check operation and the sync detection operation are performed by transport stream packets, i.e., by 8 bits×188 bytes=1504 bits, thereby requiring a delay of 1496 bits, at minimum, from the first byte to the last byte in 1 packet.
Accordingly, the decoder circuit shown in Figure B.3/J.83 employs a sequence of converting 7-bit byte data to serial bit data, performing a process using a 1497-stage delay element, and then converting the data to 8-bit byte data. Therefore, performing the entire process requires a parallel-to-serial conversion circuit, an MPEG2 sync detection syndrome computation circuit using the 1497-stage delay element shown in Figure B.3/J.83, and a serial-to-parallel conversion circuit, whereby the circuit scale is significantly large.